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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/MoreinisMWK06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arkadiy_Morgenshtein>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Avinoam_Kolodny>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Israel_A._Wagner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Moreinis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2006.886400>
foaf:homepage <https://doi.org/10.1109/TVLSI.2006.886400>
dc:identifier DBLP journals/tvlsi/MoreinisMWK06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2006.886400 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arkadiy_Morgenshtein>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Avinoam_Kolodny>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Israel_A._Wagner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Moreinis>
swrc:number 11 (xsd:string)
swrc:pages 1276-1281 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/MoreinisMWK06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/MoreinisMWK06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#MoreinisMWK06>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2006.886400>
dc:title Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 14 (xsd:string)