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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/MurugavelR03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashok_K._Murugavel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/N._Ranganathan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2003.817110>
foaf:homepage <https://doi.org/10.1109/TVLSI.2003.817110>
dc:identifier DBLP journals/tvlsi/MurugavelR03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2003.817110 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Petri net modeling of gate and interconnect delays for power estimation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashok_K._Murugavel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/N._Ranganathan>
swrc:number 5 (xsd:string)
swrc:pages 921-927 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/MurugavelR03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/MurugavelR03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi11.html#MurugavelR03>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2003.817110>
dc:title Petri net modeling of gate and interconnect delays for power estimation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 11 (xsd:string)