Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tvlsi/NakamuraCSF07
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Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
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Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.
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