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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/PomeranzR01a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F92.953501>
foaf:homepage <https://doi.org/10.1109/92.953501>
dc:identifier DBLP journals/tvlsi/PomeranzR01a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F92.953501 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
swrc:number 5 (xsd:string)
swrc:pages 679-689 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/PomeranzR01a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/PomeranzR01a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi9.html#PomeranzR01a>
rdfs:seeAlso <https://doi.org/10.1109/92.953501>
dc:title Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 9 (xsd:string)