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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/Potestad-Ordonez17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Carlos_Jes%E2%88%9A%C4%BCs_Jim%E2%88%9A%C2%A9nez-Fern%E2%88%9A%C2%B0ndez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francisco_Eugenio_Potestad-Ord%E2%88%9A%E2%89%A5%E2%88%9A%C4%AAez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manuel_Valencia-Barrero>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2017.2751151>
foaf:homepage <https://doi.org/10.1109/TVLSI.2017.2751151>
dc:identifier DBLP journals/tvlsi/Potestad-Ordonez17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2017.2751151 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Vulnerability Analysis of Trivium FPGA Implementations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Carlos_Jes%E2%88%9A%C4%BCs_Jim%E2%88%9A%C2%A9nez-Fern%E2%88%9A%C2%B0ndez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francisco_Eugenio_Potestad-Ord%E2%88%9A%E2%89%A5%E2%88%9A%C4%AAez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manuel_Valencia-Barrero>
swrc:number 12 (xsd:string)
swrc:pages 3380-3389 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/Potestad-Ordonez17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/Potestad-Ordonez17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#Potestad-Ordonez17>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2017.2751151>
dc:title Vulnerability Analysis of Trivium FPGA Implementations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 25 (xsd:string)