Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tvlsi/RatkovicPSUCV18
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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
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Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
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