An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tvlsi/RyuLLKPPLL20
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/RyuLLKPPLL20
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Han_Su_Pae
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hyun-Wook_Lim
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jae-Youl_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jinho_Kim
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jung-Pil_Lim
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Junho_Park
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kil-Hoon_Lee
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kyungho_Ryu
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2020.3018794
>
foaf:
homepage
<
https://doi.org/10.1109/TVLSI.2020.3018794
>
dc:
identifier
DBLP journals/tvlsi/RyuLLKPPLL20
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FTVLSI.2020.3018794
(xsd:string)
dcterms:
issued
2020
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tvlsi
>
rdfs:
label
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Han_Su_Pae
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hyun-Wook_Lim
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jae-Youl_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jinho_Kim
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jung-Pil_Lim
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Junho_Park
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kil-Hoon_Lee
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kyungho_Ryu
>
swrc:
number
11
(xsd:string)
swrc:
pages
2257-2267
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/RyuLLKPPLL20/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tvlsi/RyuLLKPPLL20
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#RyuLLKPPLL20
>
rdfs:
seeAlso
<
https://doi.org/10.1109/TVLSI.2020.3018794
>
dc:
title
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
28
(xsd:string)