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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/SathanurBMMP11a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashoka_Visweswara_Sathanur>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2009.2035448>
foaf:homepage <https://doi.org/10.1109/TVLSI.2009.2035448>
dc:identifier DBLP journals/tvlsi/SathanurBMMP11a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2009.2035448 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashoka_Visweswara_Sathanur>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Benini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
swrc:number 3 (xsd:string)
swrc:pages 469-482 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/SathanurBMMP11a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/SathanurBMMP11a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#SathanurBMMP11a>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2009.2035448>
dc:title Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 19 (xsd:string)