Design and Applications of Approximate Circuits by Gate-Level Pruning.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tvlsi/SchlachterCPE17
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/SchlachterCPE17
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Christian_C._Enz
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jeremy_Schlachter
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Krishna_V._Palem
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Vincent_Camus
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2017.2657799
>
foaf:
homepage
<
https://doi.org/10.1109/TVLSI.2017.2657799
>
dc:
identifier
DBLP journals/tvlsi/SchlachterCPE17
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FTVLSI.2017.2657799
(xsd:string)
dcterms:
issued
2017
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tvlsi
>
rdfs:
label
Design and Applications of Approximate Circuits by Gate-Level Pruning.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Christian_C._Enz
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Jeremy_Schlachter
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Krishna_V._Palem
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Vincent_Camus
>
swrc:
number
5
(xsd:string)
swrc:
pages
1694-1702
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/SchlachterCPE17/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tvlsi/SchlachterCPE17
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#SchlachterCPE17
>
rdfs:
seeAlso
<
https://doi.org/10.1109/TVLSI.2017.2657799
>
dc:
title
Design and Applications of Approximate Circuits by Gate-Level Pruning.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
25
(xsd:string)