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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/ShinGDG08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_Gerstlauer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Gajski>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dongwan_Shin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rainer_D%E2%88%9A%E2%88%82mer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2007.915390>
foaf:homepage <https://doi.org/10.1109/TVLSI.2007.915390>
dc:identifier DBLP journals/tvlsi/ShinGDG08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2007.915390 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_Gerstlauer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Gajski>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dongwan_Shin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rainer_D%E2%88%9A%E2%88%82mer>
swrc:number 4 (xsd:string)
swrc:pages 466-475 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/ShinGDG08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/ShinGDG08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#ShinGDG08>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2007.915390>
dc:title An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)