A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/M._Sultan_M._Siddiqui>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Tony_Tae-Hyoung_Kim>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zhao_Chuan_Lee>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2021.3102675>
foaf:homepage	<https://doi.org/10.1109/TVLSI.2021.3102675>
dc:identifier	DBLP journals/tvlsi/SiddiquiLK21 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FTVLSI.2021.3102675 (xsd:string)
dcterms:issued	2021 (xsd:gYear)
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rdfs:label	A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/M._Sultan_M._Siddiqui>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Tony_Tae-Hyoung_Kim>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Zhao_Chuan_Lee>
swrc:number	10 (xsd:string)
swrc:pages	1707-1719 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/SiddiquiLK21/dblp>
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#SiddiquiLK21>
rdfs:seeAlso	<https://doi.org/10.1109/TVLSI.2021.3102675>
dc:title	A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI. (xsd:string)
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