Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tvlsi/VemuriK95
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1995
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Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming.
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Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming.
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