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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/WangW17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Nung_Wei>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2017.2723020>
foaf:homepage <https://doi.org/10.1109/TVLSI.2017.2723020>
dc:identifier DBLP journals/tvlsi/WangW17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2017.2723020 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinn-Shyan_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Nung_Wei>
swrc:number 10 (xsd:string)
swrc:pages 2893-2906 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/WangW17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/WangW17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#WangW17>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2017.2723020>
dc:title Process/Voltage/Temperature-Variation-Aware Design and Comparative Study of Transition-Detector-Based Error-Detecting Latches for Timing-Error-Resilient Pipelined Systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 25 (xsd:string)