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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/XiaoLCL22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bingwen_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinhai_Xiao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maliang_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ning_Liang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2021.3140206>
foaf:homepage <https://doi.org/10.1109/TVLSI.2021.3140206>
dc:identifier DBLP journals/tvlsi/XiaoLCL22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2021.3140206 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bingwen_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinhai_Xiao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maliang_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ning_Liang>
swrc:number 3 (xsd:string)
swrc:pages 267-276 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/XiaoLCL22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/XiaoLCL22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi30.html#XiaoLCL22>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2021.3140206>
dc:title An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 30 (xsd:string)