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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/YangLC21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ai-Jia_Chuang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ching-Yuan_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Miao-Shan_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2021.3056506>
foaf:homepage <https://doi.org/10.1109/TVLSI.2021.3056506>
dc:identifier DBLP journals/tvlsi/YangLC21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2021.3056506 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ai-Jia_Chuang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ching-Yuan_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Miao-Shan_Li>
swrc:number 5 (xsd:string)
swrc:pages 883-894 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/YangLC21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/YangLC21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#YangLC21>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2021.3056506>
dc:title A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 29 (xsd:string)