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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/YaoHCY15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chia-Yu_Yao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rong-Jyi_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi-Yao_Chiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yung-Hsiang_Ho>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2014.2313131>
foaf:homepage <https://doi.org/10.1109/TVLSI.2014.2313131>
dc:identifier DBLP journals/tvlsi/YaoHCY15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2014.2313131 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chia-Yu_Yao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rong-Jyi_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi-Yao_Chiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yung-Hsiang_Ho>
swrc:number 3 (xsd:string)
swrc:pages 567-574 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/YaoHCY15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/YaoHCY15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#YaoHCY15>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2014.2313131>
dc:title Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)