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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/YinLXLW18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianyi_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhicong_Xie>
foaf:homepage <http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2862388>
foaf:homepage <http://dx.doi.org/10.1109%2FTVLSI.2018.2862388>
dc:identifier DBLP journals/tvlsi/YinLXLW18 (xsd:string)
dc:identifier DOI 10.1109%2FTVLSI.2018.2862388 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianyi_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhicong_Xie>
swrc:number 11 (xsd:string)
swrc:pages 2345-2357 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/YinLXLW18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/YinLXLW18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YinLXLW18>
rdfs:seeAlso <http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2862388>
dc:title Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 26 (xsd:string)