Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/vlsi/GhoneimaIKD07
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Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.
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Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.
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