Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/vlsisp/CantineauPL98
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dcterms:
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1998
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Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit.
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3
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swrc:
pages
251-265
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Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit.
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