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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/GangulyLP97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daksh_Lehther>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satyamurthy_Pullela>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shantanu_Ganguly>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1007991007969>
foaf:homepage <https://doi.org/10.1023/A:1007991007969>
dc:identifier DBLP journals/vlsisp/GangulyLP97 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1007991007969 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Clock Distribution Methodology for PowerPCTM Microprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daksh_Lehther>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satyamurthy_Pullela>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shantanu_Ganguly>
swrc:number 2-3 (xsd:string)
swrc:pages 181-189 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/GangulyLP97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/GangulyLP97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp16.html#GangulyLP97>
rdfs:seeAlso <https://doi.org/10.1023/A:1007991007969>
dc:title Clock Distribution Methodology for PowerPCTM Microprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)