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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/GironesCCS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Angel_Sebasti%E2%88%9A%E2%80%A0-Cort%E2%88%9A%C2%A9s>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joaqu%E2%88%9A%E2%89%A0n_Cerd%E2%88%9A%C2%B0-Boluda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rafael_Gadea_Giron%E2%88%9A%C2%A9s>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ricardo_Jos%E2%88%9A%C2%A9_Colom-Palero>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-005-4961-3>
foaf:homepage <https://doi.org/10.1007/s11265-005-4961-3>
dc:identifier DBLP journals/vlsisp/GironesCCS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-005-4961-3 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label FPGA Implementation of a Pipelined On-Line Backpropagation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Angel_Sebasti%E2%88%9A%E2%80%A0-Cort%E2%88%9A%C2%A9s>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joaqu%E2%88%9A%E2%89%A0n_Cerd%E2%88%9A%C2%B0-Boluda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rafael_Gadea_Giron%E2%88%9A%C2%A9s>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ricardo_Jos%E2%88%9A%C2%A9_Colom-Palero>
swrc:number 2 (xsd:string)
swrc:pages 189-213 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/GironesCCS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/GironesCCS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp40.html#GironesCCS05>
rdfs:seeAlso <https://doi.org/10.1007/s11265-005-4961-3>
dc:subject FPGA implementation; Artificial Neural Networks (ANN); backpropagation algorithm; VLSI systolic architecture (xsd:string)
dc:title FPGA Implementation of a Pipelined On-Line Backpropagation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 40 (xsd:string)