Pipelined Architecture for Additive Range Reduction.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/vlsisp/JaimeVHZ08
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Value
dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/JaimeVHZ08
>
dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Emilio_L._Zapata
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dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Francisco_J._Jaime
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dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Javier_Hormigo
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Julio_Villalba
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foaf:
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http://dx.doi.org/doi.org%2F10.1007%2Fs11265-008-0166-x
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dc:
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DBLP journals/vlsisp/JaimeVHZ08
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dc:
identifier
DOI doi.org%2F10.1007%2Fs11265-008-0166-x
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dcterms:
issued
2008
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swrc:
journal
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https://dblp.l3s.de/d2r/resource/journals/vlsisp
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rdfs:
label
Pipelined Architecture for Additive Range Reduction.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Emilio_L._Zapata
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Francisco_J._Jaime
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foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Javier_Hormigo
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foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Julio_Villalba
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swrc:
number
1-2
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swrc:
pages
103-112
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owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/JaimeVHZ08/dblp
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http://dblp.rkbexplorer.com/id/journals/vlsisp/JaimeVHZ08
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rdfs:
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http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp53.html#JaimeVHZ08
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rdfs:
seeAlso
<
https://doi.org/10.1007/s11265-008-0166-x
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dc:
subject
pipelined architecture; range reduction; modular arithmetic; floating-point; redundant arithmetic
(xsd:string)
dc:
title
Pipelined Architecture for Additive Range Reduction.
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53
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