An efficient bit-level systolic cell design for finite ring digital signal processing applications.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/vlsisp/JullienBCTM89
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1989
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An efficient bit-level systolic cell design for finite ring digital signal processing applications.
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An efficient bit-level systolic cell design for finite ring digital signal processing applications.
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