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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/JungYH08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hoeseok_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hyunuk_Jung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soonhoi_Ha>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-007-0070-9>
foaf:homepage <https://doi.org/10.1007/s11265-007-0070-9>
dc:identifier DBLP journals/vlsisp/JungYH08 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-007-0070-9 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hoeseok_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hyunuk_Jung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Soonhoi_Ha>
swrc:number 1 (xsd:string)
swrc:pages 13-34 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/JungYH08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/JungYH08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp52.html#JungYH08>
rdfs:seeAlso <https://doi.org/10.1007/s11265-007-0070-9>
dc:subject HW/SW codesign; system level design; dataflow graph (DFG); RTL; VHDL (xsd:string)
dc:title Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 52 (xsd:string)