[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/KangLS01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiyang_Kang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jongbok_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wonyong_Sung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1008155718930>
foaf:homepage <https://doi.org/10.1023/A:1008155718930>
dc:identifier DBLP journals/vlsisp/KangLS01 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1008155718930 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiyang_Kang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jongbok_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wonyong_Sung>
swrc:number 3 (xsd:string)
swrc:pages 297-312 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/KangLS01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/KangLS01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp27.html#KangLS01>
rdfs:seeAlso <https://doi.org/10.1023/A:1008155718930>
dc:subject digital signal processor; code converter; compiler-friendly; architecture synthesis; performance evaluation (xsd:string)
dc:title A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)