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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/LeeL07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soon-Chieh_Lim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sze_Wei_Lee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-006-0042-5>
foaf:homepage <https://doi.org/10.1007/s11265-006-0042-5>
dc:identifier DBLP journals/vlsisp/LeeL07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-006-0042-5 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Soon-Chieh_Lim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sze_Wei_Lee>
swrc:number 3 (xsd:string)
swrc:pages 201-221 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/LeeL07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/LeeL07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp47.html#LeeL07>
rdfs:seeAlso <https://doi.org/10.1007/s11265-006-0042-5>
dc:subject 2-D DWT processing systems; memory mapping scheme; memeory access; memory bandwidth (xsd:string)
dc:title An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 47 (xsd:string)