A four megabit Dynamic Systolic Associative Memory chip. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/G._Jack_Lipovski>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1007%2FBF00930617>
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dc:identifier	DBLP journals/vlsisp/Lipovski92 (xsd:string)
dc:identifier	DOI doi.org%2F10.1007%2FBF00930617 (xsd:string)
dcterms:issued	1992 (xsd:gYear)
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rdfs:label	A four megabit Dynamic Systolic Associative Memory chip. (xsd:string)
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swrc:pages	37-51 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1007/BF00930617>
dc:title	A four megabit Dynamic Systolic Associative Memory chip. (xsd:string)
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