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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/Meyer-BaseGT01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Antonio_Garc%E2%88%9A%E2%89%A0a_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fred_J._Taylor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uwe_Meyer-B%E2%88%9A%C2%A7se>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1008167323437>
foaf:homepage <https://doi.org/10.1023/A:1008167323437>
dc:identifier DBLP journals/vlsisp/Meyer-BaseGT01 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1008167323437 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Antonio_Garc%E2%88%9A%E2%89%A0a_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fred_J._Taylor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uwe_Meyer-B%E2%88%9A%C2%A7se>
swrc:number 1-2 (xsd:string)
swrc:pages 115-128 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/Meyer-BaseGT01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/Meyer-BaseGT01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp28.html#Meyer-BaseGT01>
rdfs:seeAlso <https://doi.org/10.1023/A:1008167323437>
dc:subject field-programmable logic (FPL); field programmable gate array (FPGA); complex programmable logic devices (CPLD); digital signal processing (DSP); residue number system (RNS); channelizer; zero-IF filter (xsd:string)
dc:title Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 28 (xsd:string)