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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/PitkanenTMT09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jarmo_Takala>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jarno_K._Tanskanen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Risto_M%E2%88%9A%C2%A7kinen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teemu_Pitk%E2%88%9A%C2%A7nen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-008-0173-y>
foaf:homepage <https://doi.org/10.1007/s11265-008-0173-y>
dc:identifier DBLP journals/vlsisp/PitkanenTMT09 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-008-0173-y (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Parallel Memory Architecture for Application-Specific Instruction-Set Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jarmo_Takala>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jarno_K._Tanskanen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Risto_M%E2%88%9A%C2%A7kinen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Teemu_Pitk%E2%88%9A%C2%A7nen>
swrc:number 1 (xsd:string)
swrc:pages 21-32 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/PitkanenTMT09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/PitkanenTMT09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp57.html#PitkanenTMT09>
rdfs:seeAlso <https://doi.org/10.1007/s11265-008-0173-y>
dc:subject Parallel memory; Low power; TTA; ASIP; Transport triggered architecture; Application-specific instruction-set processors (xsd:string)
dc:title Parallel Memory Architecture for Application-Specific Instruction-Set Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 57 (xsd:string)