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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/QiuBT09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_D._Turney>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wael_M._Badawy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yifeng_Qiu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-008-0267-6>
foaf:homepage <https://doi.org/10.1007/s11265-008-0267-6>
dc:identifier DBLP journals/vlsisp/QiuBT09 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-008-0267-6 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_D._Turney>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wael_M._Badawy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yifeng_Qiu>
swrc:number 2 (xsd:string)
swrc:pages 123-137 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/QiuBT09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/QiuBT09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp57.html#QiuBT09>
rdfs:seeAlso <https://doi.org/10.1007/s11265-008-0267-6>
dc:subject H.264/AVC; Video codec; Architecture; Multi-core; Accelerator; Virtual socket; Motion estimation; DCT/Q; IDCT/Q-1; CAVLC; Deblocking (xsd:string)
dc:title An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 57 (xsd:string)