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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/RichterF05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerhard_P._Fettweis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_Richter>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FB%3AVLSI.0000047278.94280.c3>
foaf:homepage <https://doi.org/10.1023/B:VLSI.0000047278.94280.c3>
dc:identifier DBLP journals/vlsisp/RichterF05 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FB%3AVLSI.0000047278.94280.c3 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Interleaving on Parallel DSP Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerhard_P._Fettweis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_Richter>
swrc:number 1-2 (xsd:string)
swrc:pages 161-173 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/RichterF05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/RichterF05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp39.html#RichterF05>
rdfs:seeAlso <https://doi.org/10.1023/B:VLSI.0000047278.94280.c3>
dc:subject interleaver; DSP; digital signal processor; parallel architectures; algorithm mapping (xsd:string)
dc:title Interleaving on Parallel DSP Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 39 (xsd:string)