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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/SimaCEVV05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos_T._J._van_Eijndhoven>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kees_A._Vissers>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mihai_Sima>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sorin_Cotofana>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-005-4840-y>
foaf:homepage <https://doi.org/10.1007/s11265-005-4840-y>
dc:identifier DBLP journals/vlsisp/SimaCEVV05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-005-4840-y (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label IEEE-Compliant IDCT on FPGA-Augmented TriMedia. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos_T._J._van_Eijndhoven>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kees_A._Vissers>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mihai_Sima>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sorin_Cotofana>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis>
swrc:number 3 (xsd:string)
swrc:pages 195-212 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/SimaCEVV05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/SimaCEVV05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp39.html#SimaCEVV05>
rdfs:seeAlso <https://doi.org/10.1007/s11265-005-4840-y>
dc:subject configurable computing; VLIW processor; field-programmable gate array; inverse discrete cosine transform (xsd:string)
dc:title IEEE-Compliant IDCT on FPGA-Augmented TriMedia. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 39 (xsd:string)