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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/SuchaHHS07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Antonin_Hermanek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jan_Schier>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Premysl_Sucha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zdenek_Hanz%E2%88%9A%C2%B0lek>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-006-0004-y>
foaf:homepage <https://doi.org/10.1007/s11265-006-0004-y>
dc:identifier DBLP journals/vlsisp/SuchaHHS07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-006-0004-y (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Antonin_Hermanek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jan_Schier>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Premysl_Sucha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zdenek_Hanz%E2%88%9A%C2%B0lek>
swrc:number 1 (xsd:string)
swrc:pages 35-53 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/SuchaHHS07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/SuchaHHS07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp46.html#SuchaHHS07>
rdfs:seeAlso <https://doi.org/10.1007/s11265-006-0004-y>
dc:subject high-level synthesis; cyclic scheduling; iterative algorithms; imperfectly nested loops; integer linear programming; FPGA; VLSI design; blind equalization; implementation (xsd:string)
dc:title Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 46 (xsd:string)