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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/TietcheRD15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bruce_Denby>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Brunel_Happi_Tietche>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Olivier_Romain>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-013-0840-5>
foaf:homepage <https://doi.org/10.1007/s11265-013-0840-5>
dc:identifier DBLP journals/vlsisp/TietcheRD15 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-013-0840-5 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bruce_Denby>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Brunel_Happi_Tietche>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Olivier_Romain>
swrc:number 2 (xsd:string)
swrc:pages 147-154 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/TietcheRD15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/TietcheRD15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp78.html#TietcheRD15>
rdfs:seeAlso <https://doi.org/10.1007/s11265-013-0840-5>
dc:title A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 78 (xsd:string)