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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/VanHL16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lan-Da_Van>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Po-Yen_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tsung-Che_Lu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-015-0988-2>
foaf:homepage <https://doi.org/10.1007/s11265-015-0988-2>
dc:identifier DBLP journals/vlsisp/VanHL16 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-015-0988-2 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lan-Da_Van>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Po-Yen_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tsung-Che_Lu>
swrc:number 1 (xsd:string)
swrc:pages 91-113 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/VanHL16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/VanHL16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp82.html#VanHL16>
rdfs:seeAlso <https://doi.org/10.1007/s11265-015-0988-2>
dc:title Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 82 (xsd:string)