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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/vlsisp/WoodsMM08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_G._McWhirter>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_V._McCanny>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roger_F._Woods>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11265-007-0132-z>
foaf:homepage <https://doi.org/10.1007/s11265-007-0132-z>
dc:identifier DBLP journals/vlsisp/WoodsMM08 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11265-007-0132-z (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/vlsisp>
rdfs:label From Bit Level Systolic Arrays to HDTV Processor Chips. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_G._McWhirter>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_V._McCanny>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roger_F._Woods>
swrc:number 1-2 (xsd:string)
swrc:pages 35-49 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/vlsisp/WoodsMM08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/vlsisp/WoodsMM08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp53.html#WoodsMM08>
rdfs:seeAlso <https://doi.org/10.1007/s11265-007-0132-z>
dc:subject systolic arrays; SoC architectures; DSP systems; pipelining (xsd:string)
dc:title From Bit Level Systolic Arrays to HDTV Processor Chips. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 53 (xsd:string)