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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/wpc/GavaskarMRPRS23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/B._Sanjay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Malathi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/G._Ravivarma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._Gavaskar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._S._Priyatharshan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Rajeshwari>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11277-022-10006-7>
foaf:homepage <https://doi.org/10.1007/s11277-022-10006-7>
dc:identifier DBLP journals/wpc/GavaskarMRPRS23 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11277-022-10006-7 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/wpc>
rdfs:label Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/B._Sanjay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._Malathi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/G._Ravivarma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._Gavaskar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._S._Priyatharshan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Rajeshwari>
swrc:number 2 (xsd:string)
swrc:pages 1417-1435 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/wpc/GavaskarMRPRS23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/wpc/GavaskarMRPRS23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/wpc/wpc128.html#GavaskarMRPRS23>
rdfs:seeAlso <https://doi.org/10.1007/s11277-022-10006-7>
dc:title Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 128 (xsd:string)