Architecture and Performance Analysis of a Multi-Generation SDRAM Controller for Mixed Criticality Systems (Architektur- und Leistungsanalyse eines Mehgenerationen-SDRAM-Controllers f√ľr gemischte Kritikalit√§tssysteme) | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Leonardo_Luiz_Ecco>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.24355%2Fdbbs.084-201811081233-0>
foaf:homepage	<https://doi.org/10.24355/dbbs.084-201811081233-0>
dc:identifier	DBLP phd/basesearch/Ecco18 (xsd:string)
dc:identifier	DOI doi.org%2F10.24355%2Fdbbs.084-201811081233-0 (xsd:string)
dcterms:issued	2018 (xsd:gYear)
rdfs:label	Architecture and Performance Analysis of a Multi-Generation SDRAM Controller for Mixed Criticality Systems (Architektur- und Leistungsanalyse eines Mehgenerationen-SDRAM-Controllers f√ľr gemischte Kritikalit√§tssysteme) (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Leonardo_Luiz_Ecco>
dc:publisher	Braunschweig University of Technology, Germany (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.24355/dbbs.084-201811081233-0>
dc:title	Architecture and Performance Analysis of a Multi-Generation SDRAM Controller for Mixed Criticality Systems (Architektur- und Leistungsanalyse eines Mehgenerationen-SDRAM-Controllers f√ľr gemischte Kritikalit√§tssysteme) (xsd:string)
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