A tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/phd/basesearch/Manet10
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2010
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A tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms.
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Catholic University of Louvain, Louvain-la-Neuve, Belgium
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A tile-based processor architecture model for high-efficiency embedded homogeneous multicore platforms.
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