![[RDF data]](https://dblp.l3s.de/d2r/snorql/rdf_flyer.24.gif)
| Property | Value |
|---|---|
| dcterms:bibliographicCitation | <http://dblp.uni-trier.de/rec/bibtex/phd/es/Illescas22> |
| dc:creator | <https://dblp.l3s.de/d2r/resource/authors/Pedro_Benedicte_Illescas> |
| foaf:homepage | <http://hdl.handle.net/10803/674151> |
| dc:identifier | DBLP phd/es/Illescas22 (xsd:string) |
| dcterms:issued | 2022 (xsd:gYear) |
| rdfs:label | Smart hardware designs for probabilistically-analyzable processor architectures. (xsd:string) |
| foaf:maker | <https://dblp.l3s.de/d2r/resource/authors/Pedro_Benedicte_Illescas> |
| dc:publisher | Polytechnic University of Catalonia, Spain (xsd:string) |
| owl:sameAs | <http://bibsonomy.org/uri/bibtexkey/phd/es/Illescas22/dblp> |
| owl:sameAs | <http://dblp.rkbexplorer.com/id/phd/es/Illescas22> |
| rdfs:seeAlso | <http://hdl.handle.net/10803/674151> |
| dc:title | Smart hardware designs for probabilistically-analyzable processor architectures. (xsd:string) |
| dc:type | <http://purl.org/dc/dcmitype/Text> |
| rdf:type | swrc:PhDThesis |
| rdf:type | foaf:Document |