![[RDF data]](https://dblp.l3s.de/d2r/snorql/rdf_flyer.24.gif)
| Property | Value |
|---|---|
| dcterms:bibliographicCitation | <http://dblp.uni-trier.de/rec/bibtex/phd/hal/Baklouti10> |
| dc:creator | <https://dblp.l3s.de/d2r/resource/authors/Mouna_Baklouti> |
| foaf:homepage | <https://tel.archives-ouvertes.fr/tel-00527894> |
| dc:identifier | DBLP phd/hal/Baklouti10 (xsd:string) |
| dcterms:issued | 2010 (xsd:gYear) |
| rdfs:label | Méthode de conception rapide d'architecture massivement parallèle sur puce : de la modélisation à l'expérimentation sur FPGA. (A rapid design method of a massively parallel System on Chip: from modeling to FPGA implementation). (xsd:string) |
| foaf:maker | <https://dblp.l3s.de/d2r/resource/authors/Mouna_Baklouti> |
| dc:publisher | Lille University of Science and Technology, France / √Čcole nationale d'ing√©nieurs de Sfax, Tunisia (xsd:string) |
| owl:sameAs | <http://bibsonomy.org/uri/bibtexkey/phd/hal/Baklouti10/dblp> |
| owl:sameAs | <http://dblp.rkbexplorer.com/id/phd/hal/Baklouti10> |
| rdfs:seeAlso | <https://tel.archives-ouvertes.fr/tel-00527894> |
| dc:title | Méthode de conception rapide d'architecture massivement parallèle sur puce : de la modélisation à l'expérimentation sur FPGA. (A rapid design method of a massively parallel System on Chip: from modeling to FPGA implementation). (xsd:string) |
| dc:type | <http://purl.org/dc/dcmitype/Text> |
| rdf:type | swrc:PhDThesis |
| rdf:type | foaf:Document |