Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory. (Contr√īle Autonomique du Parall√©lisme et du Placement de Threads pour les M√©moires Transactionnelles Logicielles).
Resource URI: https://dblp.l3s.de/d2r/resource/publications/phd/hal/Zhou16
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/phd/hal/Zhou16
>
dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Naweiluo_Zhou
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https://tel.archives-ouvertes.fr/tel-01408450
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DBLP phd/hal/Zhou16
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dcterms:
issued
2016
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rdfs:
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Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory. (Contr√īle Autonomique du Parall√©lisme et du Placement de Threads pour les M√©moires Transactionnelles Logicielles).
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https://dblp.l3s.de/d2r/resource/authors/Naweiluo_Zhou
>
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INRIA, France
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https://tel.archives-ouvertes.fr/tel-01408450
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dc:
title
Autonomic Thread Parallelism and Mapping Control for Software Transactional Memory. (Contr√īle Autonomique du Parall√©lisme et du Placement de Threads pour les M√©moires Transactionnelles Logicielles).
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