Wire level encapsulation framework for increasing FPGA design productivity
Resource URI: https://dblp.l3s.de/d2r/resource/publications/phd/sg/Oliver09
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/phd/sg/Oliver09
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Timothy_F._Oliver
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.32657%2F10356%2F19266
>
foaf:
homepage
<
https://doi.org/10.32657/10356/19266
>
dc:
identifier
DBLP phd/sg/Oliver09
(xsd:string)
dc:
identifier
DOI doi.org%2F10.32657%2F10356%2F19266
(xsd:string)
dcterms:
issued
2009
(xsd:gYear)
rdfs:
label
Wire level encapsulation framework for increasing FPGA design productivity
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Timothy_F._Oliver
>
dc:
publisher
Nanyang Technological University, Singapore
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/phd/sg/Oliver09/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/phd/sg/Oliver09
>
rdfs:
seeAlso
<
https://doi.org/10.32657/10356/19266
>
dc:
title
Wire level encapsulation framework for increasing FPGA design productivity
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:PhDThesis
rdf:
type
foaf:Document