Testing 3D Stacked ICs Containing Through-Silicon Vias. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Erik_Jan_Marinissen>
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dcterms:issued	2011 (xsd:gYear)
rdfs:label	Testing 3D Stacked ICs Containing Through-Silicon Vias. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Erik_Jan_Marinissen>
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dc:title	Testing 3D Stacked ICs Containing Through-Silicon Vias. (xsd:string)
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