Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs
Resource URI: https://dblp.l3s.de/d2r/resource/publications/series/lnee/BarkalovTMMK22
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/series/lnee/BarkalovTMMK22
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Alexander_Barkalov_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Elzbieta_Kawecka
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kamil_Mielcarek
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Larysa_Titarenko
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Malgorzata_Mazurkiewicz
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2F978-3-031-16027-1
>
foaf:
homepage
<
https://doi.org/10.1007/978-3-031-16027-1
>
dc:
identifier
DBLP series/lnee/BarkalovTMMK22
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2F978-3-031-16027-1
(xsd:string)
dc:
identifier
ISBN 978-3-031-16026-4
(xsd:string)
swrc:
isbn
ISBN 978-3-031-16026-4
(xsd:string)
dcterms:
issued
2022
(xsd:gYear)
rdfs:
label
Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Alexander_Barkalov_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Elzbieta_Kawecka
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kamil_Mielcarek
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Larysa_Titarenko
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Malgorzata_Mazurkiewicz
>
swrc:
pages
1-286
(xsd:string)
dc:
publisher
Springer
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/series/lnee/BarkalovTMMK22/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/series/lnee/BarkalovTMMK22
>
owl:
sameAs
<
urn:isbn:978-3-031-16026-4
>
rdfs:
seeAlso
<
http://amazon.com/s/ref=nb_ss_gw?field-keywords=978-3-031-16026-4
>
rdfs:
seeAlso
<
https://doi.org/10.1007/978-3-031-16027-1
>
dc:
title
Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Book
rdf:
type
foaf:Document
swrc:
volume
922
(xsd:string)