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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/series/synthesis/2006Reese>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitchell_A._Thornton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_B._Reese>
foaf:homepage <http://dx.doi.org/doi.org%2F10.2200%2FS00060ED1V01Y200610DCS006>
foaf:homepage <https://doi.org/10.2200/S00060ED1V01Y200610DCS006>
dc:identifier DBLP series/synthesis/2006Reese (xsd:string)
dc:identifier DOI doi.org%2F10.2200%2FS00060ED1V01Y200610DCS006 (xsd:string)
dc:identifier ISBN 978-3-031-79742-2 (xsd:string)
swrc:isbn ISBN 978-3-031-79742-2 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Introduction to Logic Synthesis using Verilog HDL (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitchell_A._Thornton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_B._Reese>
dc:publisher Morgan & Claypool Publishers (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/series/synthesis/2006Reese/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/series/synthesis/2006Reese>
owl:sameAs <urn:isbn:978-3-031-79742-2>
rdfs:seeAlso <http://amazon.com/s/ref=nb_ss_gw?field-keywords=978-3-031-79742-2>
rdfs:seeAlso <https://doi.org/10.2200/S00060ED1V01Y200610DCS006>
dc:title Introduction to Logic Synthesis using Verilog HDL (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Book
rdf:type foaf:Document