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Publication years (Num. hits)
1985-1989 (26) 1990 (18) 1991 (19) 1992 (20) 1993 (15) 1994 (155) 1995 (47) 1996 (48) 1997 (44) 1998 (49) 1999 (47) 2000 (52) 2001 (48) 2002 (78) 2003 (98) 2004 (109) 2005 (136) 2006 (140) 2007 (118) 2008 (137) 2009 (80) 2010 (46) 2011 (322) 2012 (37) 2013 (301) 2014 (42) 2015 (52) 2016 (53) 2017 (32)
Publication types (Num. hits)
article(381) book(4) incollection(5) inproceedings(1963) phdthesis(13) proceedings(3)
Venues (Conferences, Journals, ...)
ASICON(523) EDAC-ETC-EUROASIC(126) DAC(76) ISCAS(66) VLSI Design(59) ITC(43) DATE(37) IEEE Trans. VLSI Syst.(35) ASAP(29) FPL(29) ISQED(29) ICCAD(26) IEEE Trans. on CAD of Integrat...(26) ASP-DAC(25) ISPD(25) VLSI Signal Processing(25) More (+10 of total 417)
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The graphs summarize 1444 occurrences of 813 keywords

Results
Found 2372 publication records. Showing 2369 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
119Kun-Cheng Wu, Yu-Wen Tsai Structured ASIC, evolution or revolution? Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ASIC, structured ASIC
97A. Richard Newton Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
79Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng A lithography-friendly structured ASIC design approach. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ASIC, OPC, lithography
79Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano Structured/platform ASIC apprentices: which platform will survive your board room? Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF programmable ASIC platforms, digital design
72Ashutosh Chakraborty, Anurag Kumar 0002, David Z. Pan RegPlace: a high quality open-source placement framework for structured ASICs. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF global placement, regular ASIC, FPGA, placement, legalization, structured ASIC
63Ashutosh Chakraborty, David Z. Pan PASAP: power aware structured ASIC placement. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF structured ASICS, low power, placement, regular fabrics
63Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind Architecting ASIC libraries and flows in nanometer era. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF nanometer design, libraries, standard cell
62David Sheldon, Frank Vahid Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
62R. Reed Taylor, Herman Schmit Creating a power-aware structured ASIC. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF VPGA, low-power, voltage scaling, power optimization, gate sizing, structured ASIC
55Raul Camposano Will the ASIC survive? Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
55C. S. Raghu, Suravi Bhowmik, Poorvaja Ramani, S. Sundaram COST Circuit Optimization SysTem in ASIC Library Development Environment. Search on Bibsonomy VLSI Design The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
55Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
54Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak Flexible ASIC: shared masking for multiple media processors. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF optimization, interconnect, ASIC
50Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello Software-friendly HW/SW co-simulation: an industrial case study. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
49Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. Search on Bibsonomy CASES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF application synthesis, custom instruction extension, dataflow software pipeline, honeycomb, polymorphic asic, runtime reconfiguration, router, NOC
49S. Varada, V. Oduol, A. Shelat Data Flow and Buffer Management in Multi-Channel Data Link Controller. Search on Bibsonomy LCN The full citation details ... 1999 DBLP  DOI  BibTeX  RDF TDM networks, Data flow management, ASIC, Buffer management
47K. De Test methodology for embedded cores which protects intellectual property. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF core I/Os, ASIC I/O inaccessibility, partial netlist generation, ASIC level test generation, gate testing, core scan chain, selective boundary scan, coreware design paradigm, logic testing, heuristic algorithm, structural analysis, intellectual property protection, embedded cores, test methodology
47Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Beibei Ren, Anru Wang, Joyopriya Bakshi, Kai Liu, Wei Li, Wayne Wei-Ming Dai A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger, William Loh, Peter Wright Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. Search on Bibsonomy ISQED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Ranjit Yashwante, Bhalchandra Jahagirdar IEEE 1394a_2000 Physical Layer ASIC. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu Buffer design and optimization for lut-based structured ASIC design styles. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF structured asic, interconnection, buffer insertion
45P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar A highly testable ASIC for telephone signaling. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF telephone equipment, telecommunication signalling, highly testable ASIC, telephone signaling, online system diagnostic functions, integrated circuit testing, design for testability, fault simulation, application specific integrated circuits, integrated circuit design, functional simulation, digital integrated circuits, telephony
44Mark Genoe, Paul Vanoostende, Geert van Wauwe On the use of VHDL-based behavioral synthesis for telecom ASIC design. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
42David G. Chinnery, Kurt Keutzer Closing the power gap between ASIC and custom: an ASIC perspective. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF power, energy, custom, ASIC, comparison, standard cell
42David G. Chinnery, Kurt Keutzer Closing the gap between ASIC and custom: an ASIC perspective. Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF custom, ASIC, comparison, clock frequency, clock speed
42Steve Vinoski RISE++: A Symbolic Environment for Scan-Based Testing. Search on Bibsonomy IEEE Design & Test of Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
42Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen DSP system integration and prototyping with FPGAS. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz Understanding sources of inefficiency in general-purpose chips. Search on Bibsonomy ISCA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
40Deepak D. Sherlekar Design considerations for regular fabrics. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF structured ASIC, regular fabric
39Emran Bajrami, Maida Asic, Emir Cogo, Dino Trnka, Novica Nosovic Performance comparison of simulated annealing algorithm execution on GPU and CPU. Search on Bibsonomy MIPRO The full citation details ... 2012 DBLP  BibTeX  RDF
39Branko Kaucic, Teja Asic Improving introductory programming with Scratch? Search on Bibsonomy MIPRO The full citation details ... 2011 DBLP  BibTeX  RDF
39Vera V. Kovacevic-Vujcic, Miroslav D. Asic Stabilization of Interior-Point Methods for Linear Programming. Search on Bibsonomy Comp. Opt. and Appl. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
39Miroslav D. Asic, Vera V. Kovacevic-Vujcic, Mirjana D. Radosavljevic-Nikolic Asymptotic Behaviour of Karmarkar's Method for Linear Programming. Search on Bibsonomy Math. Program. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
39Steve Alpern, Miroslav D. Asic The search value of a network. Search on Bibsonomy Networks The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
38Eric Chesters Role of the verification team throughout the ASIC development life cycle. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF silicon validation, verification
38Yuejian Wu, Sandy Thomson, Han Sun, Chandra Bontu, Eric Hall Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC. Search on Bibsonomy SoCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
38Louis Baguena, Emmanuel Liégeon, Alexandra Bépoix, Jean-Marc Dusserre, Christophe Oustric, Philippe Bellocq, Vincent Heiries Development of on board, highly flexible, Galileo signal generator ASIC. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Zongxing Xie, Thiago Quirino, Mei-Ling Shyu, Shu-Ching Chen ASIC: Supervised Multi-class Classification using Adaptive Selection of Information Components. Search on Bibsonomy ICSC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam Equivalence Verification of FPGA and Structured ASIC Implementations. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Dan Feng, Lanxiang Chen, Lingfang Zeng, Zhongying Niu FPGA/ASIC based Cryptographic Object Store System. Search on Bibsonomy IAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
38Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo A methodology for FPGA to structured-ASIC synthesis and verification. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
38Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou A 225 MHz resonant clocked ASIC chip. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator
38Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri Improvement of ASIC Design Processes. Search on Bibsonomy VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Terry Tao Ye, Samit Chaudhuri, F. Huang, Hamid Savoj, Giovanni De Micheli Physical synthesis for ASIC datapath circuits. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
38Mely Chen Chi, Shih-Hsu Huang A Reliable Clock Tree Design Methodology for ASIC Designs. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Clock tree design, Clock tree synthesis
38Gyung-Hae Han, Hwa-Young Yi, Bum-Suk Go, Dong-Geun Lee, In-Haeng Cho, Dong-Il Oh A new ASIC for washer controller. Search on Bibsonomy ISCAS (6) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38D. Craig Wilcox, Lyndon G. Pierson, Perry J. Robertson, Edward L. Witzke, Karl Gass A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond. Search on Bibsonomy CHES The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
38Stefan Sjöholm, Lennart Lindh The need for Co-simulation in ASIC-verification. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
37Igor Dantas dos Santos Miranda, Ana Isabela Araújo Cunha ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF neural network arithmetic, neuroprocessor, ASIC
37Andrew Chang, William J. Dally Explaining the gap between ASIC and custom power: a custom perspective. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF custom circuits, normalized metrics, low power, energy efficiency, ASIC, EDA, technology scaling
37Takumi Okamoto, Tsutomu Kimoto, Naotaka Maeda Design methodology and tools for NEC electronics' structured ASIC ISSP. Search on Bibsonomy ISPD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ISSP, placement, structured ASIC, regular fabric
37Johannes Wolkerstorfer, Elisabeth Oswald, Mario Lamberger An ASIC Implementation of the AES SBoxes. Search on Bibsonomy CT-RSA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF standard-cell design, scalability, Very Large Scale Integration (VLSI), pipelining, Advanced Encryption Standard (AES), Application Specific Integrated Circuit (ASIC), inversion, finite field arithmetic
37Arun K. Majumdar, Nirav Patel Design of an ASIC for Straight Line Detection in an Image. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Hough Transform, CORDIC, ASIC Design
37Tony Tsang A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications. Search on Bibsonomy VLSI Design The full citation details ... 1998 DBLP  DOI  BibTeX  RDF circuit technique, VLSI, compiler, ASIC, deep sub-micron, ROM
37Miodrag Potkonjak, Wayne H. Wolf Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
33Herman Schmit, Amit Gupta, Radu Ciobanu Placement challenges for structured ASICs. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF field programmable gate arrays, placement, structured ASICs
33Gin-Der Wu, Zhen-Wei Zhu Chip Design of LPC-cepstrum for Speech Recognition. Search on Bibsonomy ACIS-ICIS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Yan Zhang, Jussi Roivainen, Aarne Mämmelä Clock-Gating in FPGAs: A Novel and Comparative Evaluation. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Steve Scott, Dennis Abts, John Kim, William J. Dally The BlackWidow High-Radix Clos Network. Search on Bibsonomy ISCA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems
32Lanxiang Chen, Dan Feng, Lingfang Zeng, Yu Zhang A Direction to Avoid Re-encryption in Cryptographic File Sharing. Search on Bibsonomy NPC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGA, access control, ASIC, cryptographic file system
32Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy 0001 Synthesis of application-specific highly efficient multi-mode cores for embedded systems. Search on Bibsonomy ACM Trans. Embedded Comput. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system
32Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer Efficient AES Implementations on ASICs and FPGAs. Search on Bibsonomy AES Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, Advanced Encryption Standard (AES), ASIC
32R. Reed Taylor, Herman Schmit Enabling energy efficiency in via-patterned gate array devices. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF VPGA, optimization, low-power, power, voltage scaling, structured ASIC
32David A. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee, Brian A. Clebowicz, Richard W. Hollis IV, Larry Wissel, Tad Wilder Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited). Search on Bibsonomy ISQED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF radiation tolerance, CCGA, reliability, DSP, ASIC, satellite communications, qualification
32B. Suresh, Biswadeep Chaterjee, R. Harinath Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Synthesizable RAM, Compiler Memory, ASIC library, Die Area Reduction, Testability
32Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu Functional Verification of Large ASICs. Search on Bibsonomy DAC The full citation details ... 1998 DBLP  DOI  BibTeX  RDF ASIC verification, simulation, emulation
32Zahari M. Darus, Iftekhar Ahmed, Liakot Ali A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed
30Yuqing Wu, Sofia Brenes, Tejas Totade, Shijin Joshua, Dhaval Damani, Michel Salim ASIC: algebra-based structural index comparison. Search on Bibsonomy CIKM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF XPath algebra, structural index
30Kamil Erkan Kabak, Cathal Heavey, Vincent Corbett Analysis of multiple process flows in an ASIC fab with a detailed photolithography area model. Search on Bibsonomy Winter Simulation Conference The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Huiju Cheng, Howard M. Heys Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. Search on Bibsonomy ASAP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
30Nikhil Jayakumar, Sunil P. Khatri A Predictably Low-Leakage ASIC Design Style. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Katherine Compton, Scott Hauck Automatic Design of Area-Efficient Configurable ASIC Cores. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF logic design and synthesis, Reconfigurable architecture
30Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri A Structured ASIC Design Approach Using Pass Transistor Logic. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
30Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30T. S. Ganesh, T. S. B. Sudarshan ASIC Implementation of a Unified Hardware Architecture for Non-Key Based Cryptographic Hash Primitives. Search on Bibsonomy ITCC (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Wayne Burleson, Sheng Xu Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats. Search on Bibsonomy MSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Hugo Hedberg, Joachim Neves Rodrigues, Fredrik Kristensen, Henrik Svensson, Matthias Kamuf, Viktor Öwall Teaching Digital ASIC Design to Students with Heterogeneous Previous Knowledge. Search on Bibsonomy MSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Qiu-Zhong Wu, Yi-He Sun An Integrated CAD Tool for ASIC Implementation of Multiplierless FIR Filters with Common Sub-expression Elimination Optimization. Search on Bibsonomy ESTImedia The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Chul Kim, Mike Myung-Ok Lee, Byung-Lok Cho, Kamran Eshraghian SOC-B Design and Testing Technique of IS-95C CDMA Transmitter for Measurement of Electric Field Intensity using FPGA and ASIC. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Ulrich Heinkel, Claus Mayer, Charles F. Webb, Hans Sahm, Werner Haas, Stefan Gossens An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs. Search on Bibsonomy SAMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
30Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou Energy Recovering ASIC Design. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
30Nikhil Jayakumar, Sunil P. Khatri An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF standby current, leakage current, standard cells, MTCMOS
30Michael Santarini, Sudhakar Jilla, Mark Miller, Tommy Eng, Sandeep Khanna, Kamalesh N. Ruparel, Tom Russell, Kazu Yamada Whither (or wither?) ASIC handoff? Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
30Donald B. Shaw, Dhamin Al-Khalili, Come Rozon Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. Search on Bibsonomy ISCAS (5) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
30Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens A Parallel ASIC Architecture for Efficient Fractal Image Coding. Search on Bibsonomy VLSI Signal Processing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
30Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto Clock skew reduction in ASIC logic design: a methodology for clock tree management. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
30Marc Campbell Evaluating ASIC, DSP, and RISC Architectures for Embedded Applications. Search on Bibsonomy LCTES The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
30I. Gibson, C. Amies Practical concurrent ASIC and system design and verification. Search on Bibsonomy ED&TC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
30Klaus D. Müller-Glaser, Jürgen Bortolazzi An Approach to Intelligent Assistance for the Specification of ASIC Design Using Objects and Rules. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
29Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni Pushing ASIC performance in a power envelope. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low-power, ASIC, high-performance, design optimization
29Kurt Keutzer, Sharad Malik, A. Richard Newton From ASIC to ASIP: The Next Design Discontinuity. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
29Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh Differences in ASIC, COT and processor design (panel). Search on Bibsonomy ISPD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF ASIC
29F. G. Lorca, Lounis Kessal, Didier Demigny Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. Search on Bibsonomy ICIP (2) The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Deriche filter architecture, real time edge detection, optimal edge detectors, FGGA circuits, memory size reduction, scale parameter, first order recursive filter, algorithm, ASIC, CMOS, adders, hardware implementation, IIR filters, IIR filters, software implementation, real time implementation, computation cost reduction, 1.2 micron
29Ronald Collet Which ASIC Technology Will Dominate the 1990's (Panel Abstract). Search on Bibsonomy DAC The full citation details ... 1992 DBLP  DOI  BibTeX  RDF ASIC
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