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Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )

URL (DBLP): http://dblp.uni-trier.de/db/conf/fpga

Publication years (Num. hits)
1995 (25) 1996 (23) 1997 (24) 1998 (49) 1999 (57) 2000 (41) 2001 (25) 2002 (27) 2003 (53) 2004 (68) 2005 (65) 2006 (53) 2007 (27) 2008 (47) 2009 (65) 2010 (67) 2011 (62) 2012 (57) 2013 (71) 2014 (70) 2015 (84) 2016 (68) 2017 (63)
Publication types (Num. hits)
inproceedings(1168) proceedings(23)
Venues (Conferences, Journals, ...)
FPGA(1191)
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The graphs summarize 1086 occurrences of 496 keywords

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Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Fubing Mao, Wei Zhang 0012, Bingsheng He, SiewKei Lam Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Jialiang Zhang, Jing Li Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang Accelerating Financial Market Server through Hybrid List Design (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William (Bill) J. Dally ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Shuo Wang, Yun Liang 0001 A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Atieh Lotfi, Rajesh K. Gupta RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Wei Ting Loke, Chin Yang Koay An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Jialiang Zhang, Soroosh Khoram, Jing Li Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides Hardware Synthesis of Weakly Consistent C Concurrency. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Gai Liu, Zhiru Zhang A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Minghua Shen, Guojie Luo Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Xiaoyu Ma, Dan Zhang, Derek Chiou FPGA-Accelerated Transactional Execution of Graph Workloads. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao A Machine Learning Framework for FPGA Placement (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre 120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Chi Zhang, Viktor K. Prasanna Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang A New Approach to Automatic Memory Banking using Trace-Based Address Mining. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yongming Shen, Michael Ferdman, Peter A. Milder Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Emanuele Pezzotti, Alex Iacobucci, Gregory Nash, Umer I. Cheema, Paolo Vinella, Rashid Ansari FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Girish Deshpande, Dinesh Bhatia Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Zhipeng Zhao, James C. Hoe Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Zhuolun He, Guojie Luo FPGA Acceleration for Computational Glass-Free Displays. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1George A. Constantinides FPGAs in the Cloud. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Alex Rodionov, Jonathan Rose Synchronization Constraints for Interconnect Synthesis. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Mostafa Koraei, Magnus Jahre, S. Omid Fatemi Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Andrew Ling, Jason Anderson The Role of FPGAs in Deep Learning. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Xin Fang, Stratis Ioannidis, Miriam Leeser Secure Function Evaluation Using an FPGA Overlay Architecture. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Sumanta Chaudhuri Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer Automatic Construction of Program-Optimized FPGA Memory Networks. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Mohammed Alawad, Mingjie Lin Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu An OpenCL™ Deep Learning Accelerator on Arria 10. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Andy Gean Ye, Karthik Ganesan Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Stylianos I. Venieris, Christos-Savvas Bouganis fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Haoyang Wu, Tao Wang 0004, Zhiwei Li, Boyan Ding, Xiaoguang Li, Tianfu Jiang, Jun Liu, Songwu Lu GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yanqiang Liu, Yao Li, Weilun Xiong, Meng Lai, Cheng Chen, Zhengwei Qi, Haibing Guan Scala Based FPGA Design Flow (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Ralf Salomon, Ralf Joost Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Jonathan W. Greene, Jason Helge Anderson (eds.) Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017 Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Subho S. Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Daniel Chen, Zbigniew T. Kalbarczyk, Deming Chen, Ravishankar K. Iyer ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Hayden Kwok-Hay So, John Wawrzynek OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu 0010 CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Christophe Bobda, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat, Laurent Njilla Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Dennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker, Mehdi Baradaran Tahoori Energy Efficient Scientific Computing on FPGAs using OpenCL. Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2017 DBLP  BibTeX  RDF
1Tianqi Wang, Bo Peng, Xi Jin an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai Testing FPGA Local Interconnects Based on Repeatable Configuration Modules (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Ze-ke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Xinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen High Level Synthesis of Complex Applications: An H.264 Video Decoder. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mohammed Alawad, Mingjie Lin Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Cédric Marchand 0002, Lilian Bossuet, Abdelkarim Cherkaoui Enhanced TERO-PUF Implementations and Characterization on FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hayden Kwok-Hay So, John Wawrzynek OLAF'16: Second International Workshop on Overlay Architectures for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Daolu Zha, Xi Jin, Tian Xiang An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Bingzhe Li, M. Hassan Najafi, David J. Lilja Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nachiket Kapre, Deheng Ye GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sizhuo Zhang, Hari Angepat, Derek Chiou HGum: Messaging Framework for Hardware Accelerators (Abstact Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sen Ma, Zeyad Aklah, David Andrews Just In Time Assembly of Accelerators. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jincheng Su, Fan Yang 0001, Xuan Zeng 0001, Dian Zhou Efficient Memory Partitioning for Parallel Data Access via Data Reuse. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Zhiyuan Yang, Ankur Srivastava Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Stefan Visser, Harald Homulle, Edoardo Charbon A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides A Case for Work-stealing on FPGAs with OpenCL Atomics. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Pingakshya Goswami, Dinesh Bhatia Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Derek Chiou Intel Acquires Altera: How Will the World of FPGAs be Affected? Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sayeh Sharifymoghaddam, Ali Sheikholeslami Low-Swing Signaling for FPGA Power Reduction (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shlomi Alkalay, Hari Angepat, Adrian M. Caulfield, Eric S. Chung, Oren Firestein, Michael Haselman, Stephen Heil, Kyle Holohan, Matt Humphrey, Tamás Juhász, Puneet Kaur, Sitaram Lanka, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Andrew Putnam, Raja Seera, Rimon Tadros, Jason Thong, Lisa Woods, Derek Chiou, Doug Burger Agile Co-Design for a Reconfigurable Datacenter. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David Lee, Jeffrey Draper SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Carl Ebeling, Dana How, David M. Lewis, Herman Schmit Stratix™ 10 High Performance Routable Clock Networks. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Paul Grigoras, Pavel Burovskiy, Wayne Luk CASK: Open-Source Custom Architectures for Sparse Kernels. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song, Yu Wang 0002, Huazhong Yang Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sabrina Zereen, Sundeep Lal, Mohammed Khalid, Sazzadur Chowdhury An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Gregg Baeckler HyperPipelining of High-Speed Interface Logic. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Que Yanghua, Chinnakkannu Adaikkala Raj, Harnhua Ng, Kirvy Teo, Nachiket Kapre Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Li Ting, Harri Wijaya, Nachiket Kapre Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Shih-Hao Hung, Min-Yu Tsai, Bo-Yi Huang, Chia-Heng Tu A Platform-Oblivious Approach for Heterogeneous Computing: A Case Study with Monte Carlo-based Simulation for Medical Applications. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Xitong Gao, John Wickerson, George A. Constantinides Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Girish Deshpande, Dinesh Bhatia An Activity Aware Placement Approach For 3D FPGAs (Abstract Only). Search on Bibsonomy FPGA The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
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