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Publications of "Rolf Drechsler" ( http://dblp.L3S.de/Authors/Rolf_Drechsler )

URL (Homepage):  http://www.informatik.uni-bremen.de/agra/eng/team.php  Author page on DBLP  Author page in RDF  Community of Rolf Drechsler in ASPL-2

Publication years (Num. hits)
1992-1995 (22) 1996-1997 (25) 1998-1999 (38) 2000 (20) 2001 (20) 2002 (20) 2003 (27) 2004 (19) 2005 (18) 2006 (21) 2007 (25) 2008 (28) 2009 (33) 2010 (35) 2011 (26) 2012 (33) 2013 (28) 2014 (43) 2015 (38) 2016 (44) 2017 (25)
Publication types (Num. hits)
article(111) book(11) incollection(1) inproceedings(453) phdthesis(1) proceedings(11)
Venues (Conferences, Journals, ...)
ISMVL(57) DATE(39) MBMV(29) ASP-DAC(26) IEEE Trans. on CAD of Integrat...(26) DSD(19) FDL(17) RC(16) DDECS(15) VLSI Design(15) ICCAD(14) DAC(13) ACM Great Lakes Symposium on V...(11) ISVLSI(11) Integration(10) EvoWorkshops(8) More (+10 of total 131)
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The graphs summarize 172 occurrences of 101 keywords

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Found 589 publication records. Showing 588 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Samah Mohamed Saeed, Xiaotong Cui, Robert Wille, Alwin Zulehner, Kaijie Wu 0001, Rolf Drechsler, Ramesh Karri Towards Reverse Engineering Reversible Logic. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu 0001, Ramesh Karri On the Difficulty of Inserting Trojans in Reversible Computing Architectures. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
1Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey metaSMT: focus on your application and not on solver integration. Search on Bibsonomy STTT The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Arighna Deb, Robert Wille, Oliver Keszocze, Saeideh Shirinzadeh, Rolf Drechsler Synthesis of optical circuits using binary decision diagrams. Search on Bibsonomy Integration The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli A PLiM Computer for the Internet of Things. Search on Bibsonomy IEEE Computer The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions. Search on Bibsonomy RC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zaid Al-Wardi, Robert Wille, Rolf Drechsler Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report. Search on Bibsonomy RC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Arun Chandrasekharan, Daniel Große, Rolf Drechsler ProACt: A Processor for High Performance On-demand Approximate Computing. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Jannis Stoppe, Oliver Keszocze, Maximilian Luenert, Robert Wille, Rolf Drechsler BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. Search on Bibsonomy ISVLSI The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Zaid Al-Wardi, Robert Wille, Rolf Drechsler Extensions to the Reversible Hardware Description Language SyReC. Search on Bibsonomy ISMVL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Arighna Deb, Robert Wille, Rolf Drechsler OR-Inverter Graphs for the Synthesis of Optical Circuits. Search on Bibsonomy ISMVL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Saman Froehlich, Daniel Große, Rolf Drechsler Error Bounded Exact BDD Minimization in Approximate Computing. Search on Bibsonomy ISMVL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta 0001, Rolf Drechsler Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates. Search on Bibsonomy ISMVL The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. Search on Bibsonomy FORMATS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Oliver Keszocze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler Exact routing for micro-electrode-dot-array digital microfluidic biochips. Search on Bibsonomy ASP-DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. Search on Bibsonomy ASP-DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. Search on Bibsonomy ASP-DAC The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler Endurance management for resistive Logic-In-Memory computing architectures. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Mehran Goli, Jannis Stoppe, Rolf Drechsler Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Leonard Schneider, Oliver Keszocze, Jannis Stoppe, Rolf Drechsler Effects of cell shapes on the routability of Digital Microfluidic Biochips. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler Data flow testing for virtual prototypes. Search on Bibsonomy DATE The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken Foreword. Search on Bibsonomy ETS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. Search on Bibsonomy GECCO The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Robert Wille, Rolf Drechsler Analyzing Inconsistencies in UML/OCL Models. Search on Bibsonomy Journal of Circuits, Systems, and Computers The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler Verifying the structure and behavior in UML/OCL models using satisfiability solvers. Search on Bibsonomy IET Cyper-Phys. Syst.: Theory & Appl. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler Ancilla-free synthesis of large reversible functions using binary decision diagrams. Search on Bibsonomy J. Symb. Comput. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler SyReC: A hardware description language for the specification and synthesis of reversible circuits. Search on Bibsonomy Integration The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Robert Wille, Oliver Keszocze, D. Michael Miller, Rolf Drechsler Embedding of Large Boolean Functions for Reversible Logic. Search on Bibsonomy JETC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. Search on Bibsonomy JETC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Arighna Deb, Robert Wille, Oliver Keszocze, Stefan Hillmich, Rolf Drechsler Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. Search on Bibsonomy JETC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken Complexity of reversible circuits and their quantum implementations. Search on Bibsonomy Theor. Comput. Sci. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler QMDDs: Efficient Quantum Function Representation and Manipulation. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. Search on Bibsonomy VLSI Design The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Rolf Drechsler, Jannis Stoppe Hardware/Software Co-Visualization on the Electronic System Level Using SystemC. Search on Bibsonomy VLSI Design The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler Integrating an SMT-Based ModelFinder into USE. Search on Bibsonomy MoDeVVa@MoDELS The full citation details ... 2016 DBLP  BibTeX  RDF
1Nils Przigoda, Robert Wille, Rolf Drechsler Ground setting properties for an efficient translation of OCL in SMT-based model finding. Search on Bibsonomy MoDELS The full citation details ... 2016 DBLP  BibTeX  RDF
1Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. Search on Bibsonomy FDL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler Change impact analysis for hardware designs from natural language to system level. Search on Bibsonomy FDL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Rolf Drechsler, Robert Wille (eds.) 2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016 Search on Bibsonomy FDL The full citation details ... 2016 DBLP  BibTeX  RDF
1Robert Wille, Oliver Keszocze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report. Search on Bibsonomy RC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler Equivalence checking using Gröbner bases. Search on Bibsonomy FMCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Vladimir Herdt, Hoang Minh Le 0001, Daniel Große, Rolf Drechsler ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. Search on Bibsonomy CAV (2) The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation. Search on Bibsonomy ISMVL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits. Search on Bibsonomy ISMVL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Zaid Al-Wardi, Robert Wille, Rolf Drechsler Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits. Search on Bibsonomy ISMVL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler Fault Detection in Parity Preserving Reversible Circuits. Search on Bibsonomy ISMVL The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Robert Wille, Oliver Keszocze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler BDD minimization for approximate computing. Search on Bibsonomy ASP-DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Hoang Minh Le 0001, Vladimir Herdt, Daniel Große, Rolf Drechsler Towards formal verification of real-world SystemC TLM peripheral models - a case study. Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler Quantitative timing analysis of UML activity diagrams using statistical model checking. Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler Formal verification of integer multipliers by combining Gröbner basis with logic reduction. Search on Bibsonomy DATE The full citation details ... 2016 DBLP  BibTeX  RDF
1Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler Precise error determination of approximated components in sequential circuits with model checking. Search on Bibsonomy DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli An MIG-based compiler for programmable logic-in-memory architectures. Search on Bibsonomy DAC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler Compiled symbolic simulation for systemC. Search on Bibsonomy ICCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler Approximation-aware rewriting of AIGs for error tolerant applications. Search on Bibsonomy ICCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler From biochips to quantum circuits: computer-aided design for emerging technologies. Search on Bibsonomy ICCAD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler Frame conditions in symbolic representations of UML/OCL models. Search on Bibsonomy MEMOCODE The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. Search on Bibsonomy MEMOCODE The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler Symbolic Error Metric Determination for Approximate Computing. Search on Bibsonomy MBMV The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler Multi-objective BDD optimization for RRAM based circuit design. Search on Bibsonomy DDECS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Mehran Goli, Jannis Stoppe, Rolf Drechsler AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. Search on Bibsonomy ICCD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler Guided lightweight Software test qualification for IP integration using Virtual Prototypes. Search on Bibsonomy ICCD The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. Search on Bibsonomy ETS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. Search on Bibsonomy GECCO (Companion) The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Robert Wille, Anupam Chattopadhyay, Rolf Drechsler From reversible logic to quantum circuits: Logic design for an emerging technology. Search on Bibsonomy SAMOS The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
1Cornelia S. Große, Lisa Jungmann, Rolf Drechsler Benefits of illustrations and videos for technical documentations. Search on Bibsonomy Computers in Human Behavior The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nicole Drechsler, André Sülflow, Rolf Drechsler Incorporating user preferences in many-objective optimization using relation ε-preferred. Search on Bibsonomy Natural Computing The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jannis Stoppe, Rolf Drechsler Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications. Search on Bibsonomy Sensors The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Robert Wille, Oliver Keszocze, Rolf Drechsler, Tobias Boehnisch, Alexander Kroker Scalable One-Pass Synthesis for Digital Microfluidic Biochips. Search on Bibsonomy IEEE Design & Test The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Rolf Drechsler Formal Specification Level - Concepts, Methods, and Algorithms. Search on Bibsonomy 2015   DOI  RDF
1Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta 0001, Hafizur Rahaman, Rolf Drechsler BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Rolf Drechsler, Martin Fränzle, Robert Wille Envisioning self-verification of electronic systems. Search on Bibsonomy ReCoSoC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska 0001, Rolf Drechsler Checking concurrent behavior in UML/OCL models. Search on Bibsonomy MoDELS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. Search on Bibsonomy MoDeVVa@MoDELS The full citation details ... 2015 DBLP  BibTeX  RDF
1Vladimir Herdt, Hoang Minh Le 0001, Daniel Große, Rolf Drechsler Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. Search on Bibsonomy ATVA The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler Reversible circuit rewriting with simulated annealing. Search on Bibsonomy VLSI-SoC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Zaid Al-Wardi, Robert Wille, Rolf Drechsler Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. Search on Bibsonomy RC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nabila Abdessaied, Mathias Soeken, Rolf Drechsler Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition. Search on Bibsonomy RC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Robert Wille, Rolf Drechsler Leveraging the Analysis for Invariant Independence in Formal System Models. Search on Bibsonomy DSD The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler Verification-Driven Design Across Abstraction Levels: A Case Study. Search on Bibsonomy DSD The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton Reverse Engineering with Simulation Graphs. Search on Bibsonomy FMCAD The full citation details ... 2015 DBLP  BibTeX  RDF
1Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. Search on Bibsonomy ISVLSI The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits. Search on Bibsonomy ISMVL The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. Search on Bibsonomy ISMVL The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Mathias Soeken, Julia Seiter, Rolf Drechsler Coverage of OCL Operation Specifications and Invariants. Search on Bibsonomy TAP The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Robert Wille, Oliver Keszocze, Clemens Hopfmuller, Rolf Drechsler Reverse BDD-based synthesis for splitter-free optical circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Aaron Lye, Robert Wille, Rolf Drechsler Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Judith Peters, Rolf Drechsler Analyzing and Simulating Time Descriptions from UML/MARTE CCSL. Search on Bibsonomy SyDe Summer School The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Melanie Diepenbeck, Rolf Drechsler Behavior Driven Development for Tests and Verification. Search on Bibsonomy SyDe Summer School The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Eleonora Schönborn, Rolf Drechsler Design and Synthesis of Reversible Circuits using Hardware Description Languages. Search on Bibsonomy SyDe Summer School The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Julia Seiter, Rolf Drechsler Development of Consistent Formal Models. Search on Bibsonomy SyDe Summer School The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Rolf Drechsler, Ulrich Kühne (eds.) Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015 Search on Bibsonomy SyDe Summer School The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Jannis Stoppe, Robert Wille, Rolf Drechsler Automated feature localization for dynamically generated SystemC designs. Search on Bibsonomy DATE The full citation details ... 2015 DBLP  BibTeX  RDF
1Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler A generic representation of CCSL time constraints for UML/MARTE models. Search on Bibsonomy DAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Vladimir Herdt, Hoang Minh Le 0001, Rolf Drechsler Verifying SystemC using stateful symbolic simulation. Search on Bibsonomy DAC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Oliver Keszocze, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler A General and Exact Routing Methodology for Digital Microfluidic Biochips. Search on Bibsonomy ICCAD The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
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