Search results for "add/subtract"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
49	Martín Vázquez 0001, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps	Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations.	ReConFig	2009	DBLP DOI BibTeX RDF	BCD, add/subtract, addtion, FPGA, subtraction, decimal arithmetic
44	Ayan Palchaudhuri, Anindya Sundar Dhar	FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation.	ACSSC	2019	DBLP DOI BibTeX RDF
44	De Liu, Mingjiang Wang, Shikai Zuo	Delay-optimized floating point fused add-subtract unit.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
44	Jongwook Sohn, Earl E. Swartzlander Jr.	Improved Architectures for a Fused Floating-Point Add-Subtract Unit.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
44	Jae Hong Min, Jongwook Sohn, Earl E. Swartzlander Jr.	A low-power dual-path floating-point fused add-subtract unit.	ACSCC	2012	DBLP DOI BibTeX RDF
44	Ishan A. Patil, Prasanna Palsodkar, Ajay Gurjar	Floating Point-based Universal Fused Add-Subtract Unit.	SocProS	2012	DBLP DOI BibTeX RDF
24	Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Duracková	A new algorithm for elimination of common subexpressions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
20	Warren A. Hunt Jr., Sol Swords	Centaur Technology Media Unit Verification.	CAV	2009	DBLP DOI BibTeX RDF
20	Neil Burgess	Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
20	Alireza Hodjat, David Hwang 0001, Ingrid Verbauwhede	A Scalable and High Performance Elliptic Curve Processor with Resistance to Timing Attacks.	ITCC (1)	2005	DBLP DOI BibTeX RDF	security, Elliptic Curve Cryptography, side-channel attacks, Galois fields, hardware architecture
20	Maya B. Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald G. Minnich	Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer.	FPL	2004	DBLP DOI BibTeX RDF
20	Jesús S. Aguilar-Ruiz, Jaume Bacardit, Federico Divina	Experimental Evaluation of Discretization Schemes for Rule Induction.	GECCO (1)	2004	DBLP DOI BibTeX RDF
20	Bart Adams, Philip Dutré	Interactive boolean operations on surfel-bounded solids.	ACM Trans. Graph.	2003	DBLP DOI BibTeX RDF	point-based geometry, surfels, boolean operations, free-form modeling
20	G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja	Graph Transformations for Improved Tree Height Reduction.	VLSI Design	2003	DBLP DOI BibTeX RDF
20	Amir M. Ben-Amram, Zvi Galil	Lower Bounds for Dynamic Data Structures on Algebraic RAMs.	Algorithmica	2002	DBLP DOI BibTeX RDF	Cell-probe lower bounds, Dynamic prefix sum, Union-find, Random access machine
20	Daniel J. Rosenkrantz, Lin Yu, S. S. Ravi	Efficient Construction of Minimum Makespan Schedules for Tasks with a Fixed Number of Distinct Execution Times.	Algorithmica	2001	DBLP DOI BibTeX RDF	Cell-probe lower bounds, Dynamic prefix sum, Union-find, Random access machine